Beschreibung
We are looking for a
Digital Verification Engineer (m/f)
Referenz: -en
Beginn: asap
Dauer: 12 MM++
Ort: in Styria
Branche: Herstellung von sonstigen elektronischen Bauelementen
Ihre Aufgaben:
- High level modeling, description and scripting languages (Verilog)
- Design-style and architecture development compatible with available flows/tools (Cadence)
- Design digital blocks and write block level tests;
- Regression testing including specification vs. simulation and FPGA programming
- Synthesis, optimization, simulation of net-lists including extraction / back-annotation;
- Circuit and system evaluation, assistance in V&V including production test.
Ihre Qualifikation
- Practical experience in digital and/or mixed signal circuit design
- Digital architecture and design techniques (state machines, microcontrollers)
- High level hardware description language (Verilog)
- Solid English, willing to learn German
- Ability and willingness to coach more junior colleagues
- Teamplayer
Skills:
- Hardware developer