Beschreibung
We are looking for a
Verification Engineer (m/f)
Reference: -en
Start: asap
Duration: 9 MM
Place: in Munich
Branch: Erbringung von Dienstleistungen der Informationstechnologie
Your tasks:
- Digital SOC Verification for an ASIC Chip project
Your qualifications
- Verification with Specman (UVM) with E language
- Verification of SOCs
- Development of Test-benches
- Knowledge of verrification techniques like constraint-random, assertion-based, formal, UVM, SystemVerilog, E
- Experience with EDA Tools
- Experience with Candence „Specman“
Skills:
- Hardware developer