Verification Engineer - Stockholm, Sweden - 12-18 Months

Vertragsart:
Vor Ort
Start:
11/2019
Dauer:
keine Angabe
Von:
Optimus Search
Ort:
Stockholm
Eingestellt:
25.01.2020
Land:
flag_no Schweden
Projekt-ID:
1881320

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Verification Engineer - Stockholm, Sweden - Immediate Start - Fluent English - 12 - 18 Months

Competence Requirements:
  • Min 7 years of advanced ASIC and/or FPGA simulation verification
  • Expertise in System Verilog UVM
  • Knowledge in VHDL and Verilog
  • Actively worked with (beneficial) or participated in Verification environment architecture definition
  • Actively worked with (beneficial) or participated (must) in Development of verification plan (Vplan).
  • Experience in VIP (Verification IP) integration
  • Experience in VIP (Verification IP) design is beneficial
  • Good System Verilog assertions knowledge
  • Good knowledge in analysis of code coverage
  • Experience in managing and debugging regressions
  • Experience in defining functional coverage items
  • Experience in evaluating regressions and mapping to Vplan
  • Experience in Clearcase beneficial


Abilities:
  • Strong analytical skills, eagerness to find innovative solutions to complex problems.
  • Can take initiatives, strong personal drive.
  • Like to work in an environment where you cooperate closely in a diverse team of colleagues, together striving to fulfil common targets.
  • Can communicate with people and find it easy to explain your findings and knowledge to others.
  • Fluent in English, speaking and writing is a must.