Beschreibung
Digital verification engineer - UVM/Cadence - 6 - 12 Months
Our client is a world leader in signal processing with video recognition and mobile device camera systems internationally. This is for a skilled and experienced verification engineer who has the ability to plan verification strategies and methodologies.
Skills Required:
- Good knowledge of verification methodologies - UVM
- VHDL, Verilog and System Verilog
- Low power design techniques
- Ability to review code
- Understanding of good coding practice
- Tools knowledge - VCS, Cadence NC, Atrenta Spyglass, Modelsim
If you are interested in this position please contact us ASAP - This is a world renown organisation that will really enhance your future career prospects!