Digital (mixed signal) verification engineer (m/f)

Beschreibung

Aufgaben:
Currently we are looking for a Digital (mixed signal) verification engineer (m/f).

Your daily tasks include:
+ The device contains a microcontroller
+ The tests are based on C and SystemVerilog/UVM
+ The analog blocks are modeled via real value models in Verilog

Jobtitel:
Digital (mixed signal) verification engineer (m/f)

Jobnummer:
38631

Stellentyp:
freiberuflich

Einsatzort:
D8, Munic

Starttermin:
asap

Dauer:
4 months +

Anforderungen:
+ Have at least 4 years experience in pre-silicon digital verification (optional AMS-verification)
+ Ability to debug complex mixed signal systems
+ Have an in-depth knowledge and project experience of SystemVerilog, Verilog, OVM, UVM and/or SVA
+ Ability to write small test programs in C
+ Have a good knowledge of Unix programming languages such as shell, Perl and Python
+ Any knowledge of mixed-signal verification would be beneficial (at real value modeling level)
+ English written and spoken

Zusätzliche Informationen:
Are you interested? Please send us your CV including the date of your availability and your hourly rate.

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