Beschreibung
Proteus Europe is searching for some UVM, System Verilog verification engineers for one of our clients in Germany. It has a choice of locations either in Central Germany or Southern Germany.
Our Client:-
Our client is an innovator in the Analog, RF and Mixed Signal ASIC Design services sector. They have in depth experience and an excellent track record providing ASIC design solutions. They work alongside many of the leading multi-national semiconductor manufacturers with ASIC design and device development.
Your New role:-
This role will use Analogue and/or Digital Verification of mixed signal ASICs based on state-of-the-art tools and FPGAs. You will be preparing Verification Plans and DFT Strategies.
You will also be working on the Test Floor and evaluate ASIC Prototypes, working on a wide range of different applications and challenging projects.
Your Skills and experience:-
Essential Skills:-
- UVM
- System Verilog
- You have experience in the development of mixed signal ASICs and/or production test development
- You have experience in design and/or verification of mixed signal ASICs
Desirable Skills:-
- Clearcase
- ASIC
- Good Team players
- Friendly personality
- You are self-motivated and self-organized
Proteus Europe operates in partnership with our candidates by building strong and lasting
relationships at all levels.
If you apply for this role, we will:
- Contact you within one week to discuss your current situation and suitability for this role.
- Keep searching for other suitable positions should this role not be right for you.
- Keep you informed at every stage of the recruitment process.
- Actively follow up with our client on your behalf to gain useful feedback throughout the
process.
If you are looking for a new role, but this role isn't quite right for you, please contact us in confidence for a discussion about how we can help you.