Beschreibung
Physical Design Engineer: Cadence, CLP, SOC-Encounter/EDIS experience
Montreal Associate's are currently conducting a search for a Physical Design Engineer for a role in Frankfurt, Germany
Tasks of a Physical Design Engineer:
IO Frame generation and validation.
Power planning, optimization, power grid and signal routing considering timing constraints
Design floor planning, analogue and memory macro placement
Place and route including timing closure
Extraction of layout parasitics and SPEF/SDF generation
Signal integrity tests
Post-synthesis static timing analysis (STA) and post-layout STA
Physical verification (DRC, ERC, LVS, ANTENNA rules)
Writing, running, optimization of scripts for above tasks
Skills needed by Physical Design Engineer:
- Desirable: Mentor Calibre
Experience with MSMV and PSO design flow desirable
Knowledge of Unix or similar operating system
Knowledge of Scripting languages (Tcl, Perl, GNU make)
Knowledge of a version control system, preferably Subversion
HDL knowledge (Verilog/VHDL)
Team player with good English communication skills
Ability to work with people from different cultures
Proactive and autonomous working style
Critical thinking, includes observation, interpretation, analysis, inference, evaluation and explanation
Able to evaluate the status and to report the task progress according to agreed milestones
Nescessary skills needed by Physical Design Engineer:
Cadence, CLP, English, EPS, ETS, Gnu Make, Perl, QRC, SOC-Encounter/EDIS, TCL/Tk, Unix, VHDL
Pefered experiences:
German, Mentor, MSMV, PSO, SubVersion
If you feel your Skills and experiences match these requirements of a Physical Design Engineer: Cadence, CLP, SOC-Encounter/EDIS experience then I would like to hear from you. Forward you updated English or German CV in Word format to me to be considered. This an English speaking Role. All Physical Design Engineer: Cadence, CLP, SOC-Encounter/EDIS experience must be able to travel and work in Europe freely without support of a Visa.