Schlagwörter
Skills
Professional profile:
Resourceful and experienced Electrical Engineer with an impressive track record of operating in the field of FPGA systems design. Engages in a strong professional development, accruing a vast array of technical proficiencies to augment over 18 years’ engineering experience; from Python to Altera Quartus to RF design. Adept at supervising diverse engineering teams in the successful completion of demanding and complex initiatives i.e. prototyping of the intel® RealSence™ 3D Camera on a Virtex7 FPGA. Multi-skilled, dynamic and passionate exponent of reverse engineering with a penchant for problem solving and mastering new skills.
Career summary:
2015-Today
DESY
Senior FPGA Engineer
Developing an innovative system for the control of Particle-Accelerator-Magnets, incorporating 10 dynamic-reconfigurable areas on a single Zynq FPGA
Performing the complete design, verification and implementation of the new generation of Particle-Detectors using a Zynq7000 FPGA. The Detectors receive data at a rate of over 30Gbps, and send it to the host over 10G Ethernet
Creating and maintaining the FPGA build-flow-automation scripting environment in Python and TCL
Building and maintaining the Embedded-Linux distribution (using Yocto), as well as writing the Linux-Drivers of the Programmable-Logic units
Conducting extensive hands-on in-lab testing using Xilinx Chipscope and electronic test instruments (oscilloscope, logic-analyzer etc.)
Functioning as a mentor to other FPGA engineers in the Institute, providing professional guidance, review and assistance with debugging of complex issues.
Performing a wide range of technical duties on a regular basis, from writing documentations and user manuals for both HW and SW to coordinating effectively with Firmware, PCB and System teams etc
2015
APPLE CORPORATION
FPGA Engineer
Responsible for the prototyping of a high-speed Imaging IP on a Xilinx Virtex7-2000 FPGA.
Involved in the prototyping of other IPs using the HAPS-60 and HAPS-70 prototyping platforms.
2012 – 2015
INTEL CORPORATION
Senior FPGA Engineer
Supervising a team of 3 FPGA engineers in the development of intel® RealSence™ 3D Camera's FPGA prototyping system to a tight deadline (MIPI D-Phy interface)
Overseeing the meticulous definition and review of design constraints to achieve timing closure on a high-speed multiple asynchronous clock domains design
Directing all activities associated with the partition of the ASIC design into 2 Xilinx Virtex7 FPGA boards, whilst designing additional Xilinx Spartan6 FPGA systems for the camera's testing boards
Prototyping of the 2D-Camera imaging IP on HAPS-70 platforms (MIPI C-Phy interface)
Successfully registering a reduction in debug count as well as increasing QOR via the integration of the FPGA design into the ASIC's UVM verification environment
2000 – 2012
GOI
2007 – 2012
FPGA & Embedded Software Engineer
Presiding over the analysis and routing of SATA communication between multiple storage systems as part of the high speed Xilinx Virtex5 FPGA system design
Overseeing the successful completion of several other projects on Altera FPGA’s
Managing the end to end development of Embedded software
Developing for numerous microcontroller types (ARM Cortex, Cygnal, TI, DSPic etc) and in numerous design environments (Keil, IAR, TI CodeComposer, Eclipse etc.)
Performing reverse engineering of embedded software
Page 2
2000 – 2007
Senior Antenna Engineer
Supervising a group of 4 antenna engineers as the Head of Antenna Research, designing a host of antennas (wire, microstrip, wide & multi band, reflector etc.) for innumerable projects
Gaining extensive experience in the design of RX chains
Performing antenna simulations using Zeland IE3D, Microwave Studio CST and TICRA GRASP8 etc.
Overseeing the development and coaching of other team members, devising and implementing new methods and design tools as part of the learning process
Refining skills in areas such as in-lab and on-field RF and Antenna measurements using test equipment (Network Analyzer, Spectrum Analyzer, Oscilloscope etc.)
1998 – 2000
RAFAEL
DSP Engineer
Developing a Matlab program to read processes and to display RADAR signals, whilst implementing tracking and identification algorithms
Identifying and eliminating various critical bugs in an existing program
Key IT Skills:
HDL: Verilog, VHDL
Languages: C, Assembly, Matlab
Scripting: Python, TCL
FPGA: Xilinx, Altera
Design tools: Xilinx Vivado&IDE, Altera Quartus Synopsys Synplify-Premier, Certify, ProtoCompiler
Simulation: Modelsim, VCS, Verdi
Revision Control: SVN, Git
OS: Linux, Windows
Microcontrollers: ARM, Cygnal, TI, DSPic etc.
Reverse Engineering: IDA pro, OllyDbg
Resourceful and experienced Electrical Engineer with an impressive track record of operating in the field of FPGA systems design. Engages in a strong professional development, accruing a vast array of technical proficiencies to augment over 18 years’ engineering experience; from Python to Altera Quartus to RF design. Adept at supervising diverse engineering teams in the successful completion of demanding and complex initiatives i.e. prototyping of the intel® RealSence™ 3D Camera on a Virtex7 FPGA. Multi-skilled, dynamic and passionate exponent of reverse engineering with a penchant for problem solving and mastering new skills.
Career summary:
2015-Today
DESY
Senior FPGA Engineer
Developing an innovative system for the control of Particle-Accelerator-Magnets, incorporating 10 dynamic-reconfigurable areas on a single Zynq FPGA
Performing the complete design, verification and implementation of the new generation of Particle-Detectors using a Zynq7000 FPGA. The Detectors receive data at a rate of over 30Gbps, and send it to the host over 10G Ethernet
Creating and maintaining the FPGA build-flow-automation scripting environment in Python and TCL
Building and maintaining the Embedded-Linux distribution (using Yocto), as well as writing the Linux-Drivers of the Programmable-Logic units
Conducting extensive hands-on in-lab testing using Xilinx Chipscope and electronic test instruments (oscilloscope, logic-analyzer etc.)
Functioning as a mentor to other FPGA engineers in the Institute, providing professional guidance, review and assistance with debugging of complex issues.
Performing a wide range of technical duties on a regular basis, from writing documentations and user manuals for both HW and SW to coordinating effectively with Firmware, PCB and System teams etc
2015
APPLE CORPORATION
FPGA Engineer
Responsible for the prototyping of a high-speed Imaging IP on a Xilinx Virtex7-2000 FPGA.
Involved in the prototyping of other IPs using the HAPS-60 and HAPS-70 prototyping platforms.
2012 – 2015
INTEL CORPORATION
Senior FPGA Engineer
Supervising a team of 3 FPGA engineers in the development of intel® RealSence™ 3D Camera's FPGA prototyping system to a tight deadline (MIPI D-Phy interface)
Overseeing the meticulous definition and review of design constraints to achieve timing closure on a high-speed multiple asynchronous clock domains design
Directing all activities associated with the partition of the ASIC design into 2 Xilinx Virtex7 FPGA boards, whilst designing additional Xilinx Spartan6 FPGA systems for the camera's testing boards
Prototyping of the 2D-Camera imaging IP on HAPS-70 platforms (MIPI C-Phy interface)
Successfully registering a reduction in debug count as well as increasing QOR via the integration of the FPGA design into the ASIC's UVM verification environment
2000 – 2012
GOI
2007 – 2012
FPGA & Embedded Software Engineer
Presiding over the analysis and routing of SATA communication between multiple storage systems as part of the high speed Xilinx Virtex5 FPGA system design
Overseeing the successful completion of several other projects on Altera FPGA’s
Managing the end to end development of Embedded software
Developing for numerous microcontroller types (ARM Cortex, Cygnal, TI, DSPic etc) and in numerous design environments (Keil, IAR, TI CodeComposer, Eclipse etc.)
Performing reverse engineering of embedded software
Page 2
2000 – 2007
Senior Antenna Engineer
Supervising a group of 4 antenna engineers as the Head of Antenna Research, designing a host of antennas (wire, microstrip, wide & multi band, reflector etc.) for innumerable projects
Gaining extensive experience in the design of RX chains
Performing antenna simulations using Zeland IE3D, Microwave Studio CST and TICRA GRASP8 etc.
Overseeing the development and coaching of other team members, devising and implementing new methods and design tools as part of the learning process
Refining skills in areas such as in-lab and on-field RF and Antenna measurements using test equipment (Network Analyzer, Spectrum Analyzer, Oscilloscope etc.)
1998 – 2000
RAFAEL
DSP Engineer
Developing a Matlab program to read processes and to display RADAR signals, whilst implementing tracking and identification algorithms
Identifying and eliminating various critical bugs in an existing program
Key IT Skills:
HDL: Verilog, VHDL
Languages: C, Assembly, Matlab
Scripting: Python, TCL
FPGA: Xilinx, Altera
Design tools: Xilinx Vivado&IDE, Altera Quartus Synopsys Synplify-Premier, Certify, ProtoCompiler
Simulation: Modelsim, VCS, Verdi
Revision Control: SVN, Git
OS: Linux, Windows
Microcontrollers: ARM, Cygnal, TI, DSPic etc.
Reverse Engineering: IDA pro, OllyDbg
Projekthistorie
1. A remote project implementing a complete wifi 802.11agn PHY in an FPGA including:
* Implementing the 802.11agn PHY TX & RX layer (qualization, frquency offset correction, de-/encoding, de/modulatoin, packet detection etc.).
* The packets are sent/received to/from the host via FX3-USB3 device over VITA protocol.
* To allow for smooth communication, a part of the MAC layer was also implemented, so ACK messages could be automatically generated and transmitted whenever necessary in the time frames described by the standard.
* Reduced project costs by successfully implementing dual channels on a low-cost Xilinx Spartan-6 FPGA.
* development of a full-chip verification environment in SystemVerilog utilizing OVM/UVM methodology, and comparing the results with a python 802.11 mathematical model.
* development of a fully-automatic TCL based scripting environment for the FPGA synthesis and implementation.
* version control in SVN
* Lab testing and support in integration and SW driver development on the host.
2. A part-remote-part-onsite project of a high speed imaging system:
* development of a high speed imaging system receiving image information from 12 sources in parallel, and sending it to the host via 10g-KR Ethernet optical link.
* Incorporating a micro-controller system in the FPGA for configuration and control, communicating with the host over 1g Ethernet 1000BASE-T link.
* Development of the microcontroller's bare-metal c code.
* development of a full-chip verification environment in SystemVerilog utilizing OVM/UVM methodology.
* development of a fully-automatic TCL based scripting environment for the FPGA synthesis and implementation.
* version control in Git
* Lab testing and cooperation with the SW and HW team.
Reisebereitschaft
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