05.12.2023 aktualisiert


100 % verfügbar
IC Validation, Post Silicon Verification, RF & IC Silicon Testing, System Integration, Component Cha
Unterhaching, Deutschland
Weltweit
Electronics EngineeringSkills
Java3D Printing4G (Telecommunication)LTE (Telekommunikation)WLANAdobe InDesignKünstliche IntelligenzAnwendungshinweiseARM ArchitekturAtlassian JiraAugmented RealityTest AutomationBluetooth Low EnergyBluetoothWcdma
3-D Printing, 4G, ARM processor, in design, Application Notes, ASIC, Artificial Intelligence, AI, Augmented Reality, automated test, Automated Testing, Automated tests, Bitbucket, Blockchain, Bluetooth, Bluetooth Low Energy, CMake, cloud-based , Data Communications, data services, Data Sheet, Data Sheets, desktop PC, Digital Circuits, Distributed Revision Control, FPGA, Firmware, Front-End, GPRS, Git, GPS, GSM, hard disk, solid-state drives, Hardware Validation, Digital Technologies, ticketing system, Jira, JSON, JAMA, Java, JTAG, LTE, LabVIEW, Lauterbach, Digital Design, Matlab, Visual Studio, GSM modem, USB modem, Multi-Protocol, NFC, OpenText, ORCAD, PCIe, microcontroller, payment system, Performance Testing, performance optimization, Development Tools, Python Programming Language, Python, Red hat Enterprise Linux, Regression testing, regression test, signal Integrity, Signal Processing, debugging, Debugger, requirements definition, version control, Source Code Management, subsystem , Sub-System, ICs, Supervisory control and data acquisition (SCADA), System Validation, system on chip, System Integration, tablets, Testcases, test-cases, Test Scripts, TestStand, Verilog, Virtual Machine, Virtual Reality, WCDMA, W -CDMA, WLAN, wireless technologies
Erfahrung
Berufserfahrungmehr als 10 Jahre
Freelancer seit2012
Sprachen
DeutschgutEnglischverhandlungssicherGriechischMuttersprache
Projekthistorie
Undertaking referred to as KDT Regulation or Single Basic Act (SBA).
**The joint undertakings have three general objectives, in accordance with Article 4 of the SBA:
* strengthening and integrating the scientific, innovation and technological capacities and
facilitating collaborative links,
* securing sustainability-driven global leadership and resilience of Union value chains in
key technologies and industries and on developing, and
* accelerating the uptake of innovative solutions throughout the Union addressing
climate, environmental, health, digital and other global challenges.
***A KDT Innovation Action (IA) primarily consists of activities aiming at technology or method
introduction, pilot lines, test beds, demonstrators, innovation pilots and zones of full-scale
testing.
**The joint undertakings have three general objectives, in accordance with Article 4 of the SBA:
* strengthening and integrating the scientific, innovation and technological capacities and
facilitating collaborative links,
* securing sustainability-driven global leadership and resilience of Union value chains in
key technologies and industries and on developing, and
* accelerating the uptake of innovative solutions throughout the Union addressing
climate, environmental, health, digital and other global challenges.
***A KDT Innovation Action (IA) primarily consists of activities aiming at technology or method
introduction, pilot lines, test beds, demonstrators, innovation pilots and zones of full-scale
testing.
The KDT Joint Undertaking is a public-private partnership that funds Research, Development and
Innovation projects in Electronic Components and Systems, engaging finances from the EU, KDT JU
Participating States and the participants (industry, academia, etc.).
KDT JU contributes to Cluster 4 of Horizon Europe.
I have been assisting the Joint Undertaking with the evaluation of the proposals submitted in response
to
the following calls for proposals:
Fotios Giannakopoulos - page 3
1. HORIZON-KDT-JU-2023-1-IA, (HORIZON-JU-IA HORIZON JU Innovation Actions)
2. HORIZON-KDT-JU-2023-2-RIA, (HORIZON-JU-RIA HORIZON JU Research and Innovation Actions)
3. HORIZON-KDT-JU-2023-3-CSA-IA, (HORIZON-JU-CSA HORIZON JU Coordination and Support
Actions)
This involves in particular, the following tasks:
- reading and analysing the background information (especially the proposal and the briefing material)
- participating in the expert briefings, meetings or webcast briefings
- participating in evaluation meetings and hearings and
- drafting and submitting the evaluation reports for the evaluated proposals and other deliverables.
Innovation projects in Electronic Components and Systems, engaging finances from the EU, KDT JU
Participating States and the participants (industry, academia, etc.).
KDT JU contributes to Cluster 4 of Horizon Europe.
I have been assisting the Joint Undertaking with the evaluation of the proposals submitted in response
to
the following calls for proposals:
Fotios Giannakopoulos - page 3
1. HORIZON-KDT-JU-2023-1-IA, (HORIZON-JU-IA HORIZON JU Innovation Actions)
2. HORIZON-KDT-JU-2023-2-RIA, (HORIZON-JU-RIA HORIZON JU Research and Innovation Actions)
3. HORIZON-KDT-JU-2023-3-CSA-IA, (HORIZON-JU-CSA HORIZON JU Coordination and Support
Actions)
This involves in particular, the following tasks:
- reading and analysing the background information (especially the proposal and the briefing material)
- participating in the expert briefings, meetings or webcast briefings
- participating in evaluation meetings and hearings and
- drafting and submitting the evaluation reports for the evaluated proposals and other deliverables.
*IC Validation Engineer of Radio Front-End (Analog/Digital) subsystem module of a next-generation
Tuner
Business Line Radio Frequency Processing (RFP)
IC Validation Tasks:
-Validation of Radio Front-End (Analog/Digital) subsystem module of a next-generation Tuner.
-Port Test cases from UVM Verification Framework to Validation Framework. Use of ARM processor (M
series and A series) / Memories(TCM/SRAM)/Peripherals Validation.
-Creation and Execution of Complex Scenarios of the Digital Part of the Radio Front End to FPGA and
Silicon Testbench according to Test Specifications and Test Requirements.
-Use Lauterbach Development Tools (Lauterbach Debugger, Trace 32 for Rd/Wr/Debugging).
-Assess the overall RFEDig Block performance (From ADC to Decimator Filters, Data Packers (PCIe
Frame Packer), Write Direct Memory Access (WDMA), AXI to APB Bridge, until the System Memory
Subsystem or another ARM-Based Processor Block).
-Test of PCIe Bus Communication between RFdig Subsystem, Memory, and several ARM-Based
Processors of the Chip.
-Compile C Code with Visual Studio and prepare Firmware for HW testing.
Fotios Giannakopoulos - page 4
-Test C code drivers ( .dll,.h, .exe, etc.) for debugging purposes and Create and run Batch Scripts for
quick automation and execution.
-Use of Quartus Prime and MAX10 FPGA as a protocol translator between PC and Prototype Boards
(e.g. Serial to AXI) and update Verilog code to match the Digital Design of the ASIC.
-Sustain Matlab Framework and Test Scripts.
-Use CMake Structures for Validation SW Build Flow.
-Drive discussions on optimization Topics and Assist Bring-up.
-Utilisation of Git version control Tool and Bitbucket as Git repository management with best-in-class
Jira integration for collaboration on source code, and guidance through the development flow.
-Work with Virtual Machine Environment (Exceed TurboX Client by OpenText) and Red hat Enterprise
Linux OS.
Product info:
The Device belongs to the BL Automotive of NXP (Analog/Digital Radio and Audio) Portfolio.
Tuner
Business Line Radio Frequency Processing (RFP)
IC Validation Tasks:
-Validation of Radio Front-End (Analog/Digital) subsystem module of a next-generation Tuner.
-Port Test cases from UVM Verification Framework to Validation Framework. Use of ARM processor (M
series and A series) / Memories(TCM/SRAM)/Peripherals Validation.
-Creation and Execution of Complex Scenarios of the Digital Part of the Radio Front End to FPGA and
Silicon Testbench according to Test Specifications and Test Requirements.
-Use Lauterbach Development Tools (Lauterbach Debugger, Trace 32 for Rd/Wr/Debugging).
-Assess the overall RFEDig Block performance (From ADC to Decimator Filters, Data Packers (PCIe
Frame Packer), Write Direct Memory Access (WDMA), AXI to APB Bridge, until the System Memory
Subsystem or another ARM-Based Processor Block).
-Test of PCIe Bus Communication between RFdig Subsystem, Memory, and several ARM-Based
Processors of the Chip.
-Compile C Code with Visual Studio and prepare Firmware for HW testing.
Fotios Giannakopoulos - page 4
-Test C code drivers ( .dll,.h, .exe, etc.) for debugging purposes and Create and run Batch Scripts for
quick automation and execution.
-Use of Quartus Prime and MAX10 FPGA as a protocol translator between PC and Prototype Boards
(e.g. Serial to AXI) and update Verilog code to match the Digital Design of the ASIC.
-Sustain Matlab Framework and Test Scripts.
-Use CMake Structures for Validation SW Build Flow.
-Drive discussions on optimization Topics and Assist Bring-up.
-Utilisation of Git version control Tool and Bitbucket as Git repository management with best-in-class
Jira integration for collaboration on source code, and guidance through the development flow.
-Work with Virtual Machine Environment (Exceed TurboX Client by OpenText) and Red hat Enterprise
Linux OS.
Product info:
The Device belongs to the BL Automotive of NXP (Analog/Digital Radio and Audio) Portfolio.