UVM Verification In SystemVerilog

Beschreibung

Verificationengineer UVM wanted

A innovative company with a state-of-the-art environment is looking for Verification specialist in UVM with Systemverilog.

Your task:

- Verification of RTL-Blocks with UVM in SystemVerilog

Your qualifications :

- Experience in UVM or OVM verification

- Experience in SystemVerilog

Fakts:

- Projectstart: asap

- Location: Northern Germany

- Duration: 4 months

- Contract: Freelance contractor

If you qualify for the above mentioned task and are willing to accept a new challenge in a top level environment, contact me as soon as possible.

Also if you know anyone of your colleagues or friends that could be suitable for this project feel free to pass on the information.