Beschreibung
We are looking for a
Physical Layout Engineer (m/f)
Referenz: -en
Beginn: asap
Dauer: 4 MM
Ort: in North Rhine-Westphalia
Branche: Elektronik
Ihre Aufgaben:
- Place and Route
- Clock Tree Synthesis
- Timing Optimization
- Power Optimization
- Static Timing Analysis
- Timing Constraints
Ihre Qualifikation
- Knowledge in digital Layout
- Cadence EDI (preferred)
- Synopsys ICC
Skills:
- Development Manager
Keywords: layout design semiconductor halbleiter microchips digital cadence synopsis