Beschreibung
*Senior IC Layout Engineer*
Duties & Responsibilities
* All Layout activities including top, cell and block level creation, edit and full verification.
* Use state-of-the-art layout techniques for matching, ESD, latch-up prevention and parasitic reduction.
* Work with an estimation of layout timescales plus any subsequent re-estimations due to design changes.
* Suggest improvements to the overall layout capabilities of Dialog Semiconductor team
* Maintain a layout workspace
Essential -
* Proven top-level layout experience including floor planning, power routing and full verification
* Demonstrable competence in 'Design for Manufacture' techniques
* Competence and expertise in providing layouts to deadline as defined by project plans
Desirable -
* Top-level team management - including coordination of block assignments and inputs from other team. Thorough knowledge of Cadence Virtuoso, VXL, Assura and Calibre
* Takes responsibility for solutions and makes them happen
* Results-oriented and able to deliver on-time under tight schedule pressures
If you are interested in the above position and have the relevant skills for the positin then please do send an up to date CV or simply click apply.
Key Words : - IC Layout, IC, Layout, DRC, LVS, Cadence, C65, CMOS, physical design, analog