Semiconductor Package Layouter

Bayern  ‐ Vor Ort
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Schlagworte

Beschreibung

Our customer is an international telecommunications company, involved in the R&D of cutting-edge mobile technologies. We currently have an exciting opportunity for a Semiconductor Package Layouter

Project Start: as soon as possible

Project duration:6-12 months

Location: Munich or Regensburg

Task Description:

  • Routing/conceptual studies for substrate based semiconductor packaging based a given chip design or floor plan studies
  • Layout of substrates for flip chip packages or rewiring of 1-layer wafer-level packages (fan-out) in chip/package co-design environment, in close coordination with Concept Engineering Concept in chip and package area
  • layout of printed circuit boards for testing purposes (daisy chain routing)

Required Skills:

  • Knowledge of Layout of Semiconductor Housing
  • Cadence tool or Mentor Graphics tool knowhow

If you are interested in this vacancy, we would be pleased to receive your CV together with your availability and financial expectations.

Start
ab sofort
Dauer
6-12 months +
(Verlängerung möglich)
Von
Harvey Nash Plc - Stuttgart
Eingestellt
13.06.2012
Projekt-ID:
376693
Vertragsart
Freiberuflich
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