Beschreibung
JWA is seeking to engage a Hardware engineer for a telecommunications project in Germany.
You will have a strong understanding of SPYGLASS and experience with RTL Digital. Exposure to test benches, simulation and validation is also needed. Applicants must either be fluent in VHDL or both Verilog and Unix.
You will be responsible for verifying Hardware for 3G modem IPs with SPYGLASS (lining and CDC)
Successful candidates will have a Masters degree in Electrical engineering (or similar)
This is a 3 month (extendable) contract. There is a very good rate available.
Please contact James Hezelgrave with an up to date version of your CV for more details.
Key Skills:
Spyglass, Verilog, VHDL, UNIX, Hardware, Germany, JWA, CDC, RTL, Test bench, Simulation, Validation