Beschreibung
Physical Design engineer is required by our prestigious multinational client
Physical Design engineer tasks will be:
IO Frame generation and validation,power planning, optimization, power grid and signal routing considering timing constraints,design floor planning, analogue and memory macro placement,place and route including timing closure,extraction of layout parasitics and SPEF/SDF generation,signal integrity tests,post-synthesis static timing analysis (STA) and post-layout STA,physical verification (DRC, ERC, LVS, ANTENNA rules)writing, running, optimization of scripts for above tasks.
Physical Design engineer skills required:
At least 5 years professional experience in microelectronics physical implementation
Experience with the following tools:
Mandatory: Cadence RTL Compiler, SOC-Encounter/EDIS, ETS, EPS
CLP, QRCm,
Desirable: Mentor Calibre,Experience with MSMV and PSO design flow desirable
Knowledge of Unix or similar operating system,knowledge of Scripting languages (Tcl, Perl, GNU make)
Knowledge of a version control system, preferably Subversion,HDL knowledge (Verilog/VHDL),Team player with good English communication skills,ability to work with people from different cultures,proactive and autonomous working style
Critical thinking, includes observation, interpretation, analysis, inference, evaluation and explanationable to evaluate the status and to report the task progress according to agreed milestones.Nescessary skills:
Cadence, CLP, English, EPS, ETS, Gnu Make, Perl, QRC, SOC-Encounter/EDIS, TCL/Tk, Unix, VHDL
Pefered experiences:
German, Mentor, MSMV, PSO, SubVersion
Consultant will be based in Germany and will be utilised till the end of June 2013
For interview slots please forward your CV asap