Beschreibung
Physical Designer - Cadence RTL Verilog VHDL
Tasks:
IO Frame generation and validation
Power planning, optimization, power grid and signal routing considering timing constraints
Design floor planning, analogue and memory macro placement
Place and route including timing closure
Extraction of layout parasitics and SPEF/SDF generation
Signal integrity tests
Post-synthesis static timing analysis (STA) and post-layout STA
Physical verification (DRC, ERC, LVS, ANTENNA rules)
Writing, running, optimization of scripts for above tasks
Skills:
At least 5 years professional experience in microelectronics physical implementation
Experience with the following tools:
- Mandatory: Cadence RTL Compiler, SOC-Encounter/EDIS, ETS, EPS
- CLP, QRC
- Desirable: Mentor Calibre
Experience with MSMV and PSO design flow desirable
Knowledge of Unix or similar operating system
Knowledge of Scripting languages (Tcl, Perl, GNU make)
Knowledge of a version control system, preferably Subversion
HDL knowledge (Verilog/VHDL)
Team player with good English communication skills
Ability to work with people from different cultures
Proactive and autonomous working style
Critical thinking, includes observation, interpretation, analysis, inference, evaluation and explanation
Able to evaluate the status and to report the task progress according to agreed milestones
Cadence,CLP,English,EPS,ETS,Gnu Make,Perl,QRC,SOC-Encounter/EDIS,TCL/Tk,Unix,VHDL
ConSol Partners is acting as the resource consultancy for this project.