Beschreibung
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Design Engineer – Testchip Integration (m/w)
Referenz: -de
Beginn: asap
Dauer: 6 MM
Ort: in Sachsen
Branche: Herstellung von sonstigen elektronischen Bauelementen
Ihre Aufgaben:
- Design Engineering in the Testchip integration group
- work with internal IP providers who contribute teststructures for various elements of the technology to use the area of the testchips as optimal as possible
- to develop teststructures on their own and to execute on the integration and final verification of testchip floorplanning, power grid generation and analysis, signal routing, chip finishing and physical
- handing over to the GlobalTapeoutOperations team for Mask-data-preparation
- support the early standard and customized MPWshuttles, where the major focus is on floorplanning and DRC support for customers, accommodating their needs and optimizing the flow for state-of-the-art cycletimes from GDS-in to Masks-in-FAB
- This task requires strong collaboration with the various global teams like Process Integration and Technology development, CE, MDP and others.
Ihre Qualifikation
- Bachelor Degree in Electrical Engineering, Computer Science or other relevant engineering disciplines is required
- Advanced skills of common design analyses tools like Calibre, Lavis, Calibredrv
- Knowledge of semiconductor design environments (like CadenceEncounter, SynopsysICC) and mask generation/tapeout flow as well as solid knowledge on physical verification tools like Calibre DRC and LVS is a pre-requisite. The knowledge of scripting languages as well as analog/mixed-signal design tools like Cadence Virtuoso would also be a good addition.
- Good verbal and written communication skills
- Strong interpersonal skills and ability to work effectively in cross-functional teams and with different cultures across different sites
- Good English language skills
Skills:
- Elektrotechnik