Beschreibung
Start: ASAPLocation: REMOTE
LOA: 3-6 months
Language: English
Skills required:
Physical Design and Implementation (Backend)
CADENCE Tools
22nm TSMC Technology
Experience with ICC2
Floor Planning, Signal Routing, Timing Closure Analysis
Experience in STA (Advantage)
Work – mostly top level, some STA, timing closures (biggest area for support)
very experienced Physical Design Engineers with +10 years experience in P&R, STA and recent experience with ICC2 and Primetime. The candidate should be able to drive a top-level implementation with tough timing signoff requirements ( mixed track libraries with different ocv methodology, additional voltage, aging derate and massive multi mode signoff strategy).