ASIC Designer - Nuremberg - ASAP Start - 70 - 90 EUR/hr

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12 Months
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ASIC Designer - Nuremberg - ASAP Start - 70 - 90 EUR/hr - 12 Months

My current client has a fast growing hardware team, and now has an exciting opportunity for an experienced ASIC designer with proven ability to deliver high quality, low power, high performance micro-architecture and RTL implementations in challenging timescales to join the team.

The key duties are:
  • Interaction with Research team on algorithm optimization.
  • Micro-architecture definition and Power Performance and Area (PPA) efficient RTL implementation of Image Processing Algorithms.
  • RTL (System Verilog/Verilog/ VHDL) and verification (UVM, system Verilog).
  • Perform ASIC Design quality checks on RTL - for example, Lint, Synthesis and Logical equivalence
  • Block level verification including but not limited to test bench, test plan and test cases creation.
  • Functional debugging of RTL on Simulator and FPGA.

The key skills are:
  • Expertise with ASIC design flow i.e. PPA efficient image algorithm Micro-architecture and RTL implementation, design quality checks, block-level verification, timing closure, size and speed optimization.
  • Hardware design skills - PPA efficient RTL Design (System Verilog/Verilog/VHDL) and industry standard verification methodologies (UVM, System Verilog).
  • Experience with Synopsys/Cadence/Mentor ASIC tools (Synthesis/Lint/LEC/Simulation/Low Power Design)
  • Basic MATLAB and C/C++ programming skills.
  • Familiarity with scripting languages, tools command-line and automation (PYTHON, PERL, TCL, BASH)

In addition, it would be helpful to have the following:
  • Knowledge of memory subsystems, AXI and system integration
  • Experience with FPGA synthesis tools (Xilinx, Altera)