Beschreibung
Proteus Europe is searching for some Verification Engineers with either System Verilog or UVM experience for one of our clients based in Germany (Various locations)Our Client :-
Our client is an innovator in the Analog, RF and Mixed Signal ASIC Design services sector. They have in depth experience and an excellent track record providing ASIC design solutions. They work alongside many of the leading multi-national semiconductor manufacturers with ASIC design and device development.
Your New role :-
Our client is looking for an experienced Verification Engineer who has either System Verilog or UVM skills to join an existing verification team who need additional assistance for a high speed data communication ASIC project.
It is a multinational team, so communication can be in either English or German depending on which language is easier for you.
Your Skills and experience :-
Essential Skills :-
- Verification
- System Verilog
- UVM
Desirable Skills :-
- ASIC
- English
Proteus Europe operates in partnership with our candidates by building strong and lasting
relationships at all levels.
If you apply for this role, we will:
- Contact you within one week to discuss your current situation and suitability for this role.
- Keep searching for other suitable positions should this role not be right for you.
- Keep you informed at every stage of the recruitment process.
- Actively follow up with our client on your behalf to gain useful feedback throughout the
process.
If you are looking for a new role, but this role isn't quite right for you, please contact us in
confidence for a discussion about how we can help you.