Beschreibung
We are looking for a PCIe Subsystem Design for the Munich, Germany Location.
Please find the below the Job Description.
Location: Munich, Germany
Duration: 5 months
Number of resources: 1 Position
No. of years Exp.- 7+ years
JD is as mentioned below.
Detailed JD -
- PCIe Subsystem Design
- Digital design with at least 8 year experience
- Generate CTRL/Subsystem and integrate it with the PHY
- Apply custom logic needed for SoC
- Experience with Low power design(multi-clock, multi-voltage, LP modes, UPF)
- Integrate the design into Intel design flow
- Spyglass analysis, Synthesis and timing check
- Support verification eng and SoC
- Ensure Intel delivery quality checks as per defined checklist
- Protocol familiarity: PCIe needed
- Proactive planning, communication and follow-up skills