ASIC RTL Design Engineer

Beschreibung

ASIC RTL Design Engineer
My client is in need of experienced and passionate ASIC RTL Design Engineers to help build and develop the front end of their ASIC platform. The client is a very well known, well established leader in the market and is worked on exciting, cutting edge technology for various different industries.
The specifics of the project I’m allowed to share is limited but they have been involved in designing and developing ground-breaking, innovative technology for the Semiconductor Industry.

This requirement is due to a ramp up and increased workload to ensure delivery deadlines are met. The start date is ASAP and the project will last up to mid-2022.
The pay rate on offer is market rate for a 100% remote working, front end Verilog based design role. As mentioned, this role is 100% remote working from start to finish, with or without the restrictions currently imposed across the world.
Responsibilities for the ASIC RTL Design Engineer:
1) Implementation of a C/C++ model using Verilog RTL language.
2) Development of interface and system control loops specifically involving fault monitoring, test access and Clock Tree Implementation.

Requirements for the ASIC RTL Design Engineer:
1) 5 years industry experience in digital design.
2) Excellent Verilog coding skills.
a. Familiar with large mixed signal SOC designs using APB bus is a bonus.
3) Excellent communication skills, verbal & email.

If you’re interested in this ASIC RTL Design Engineer position or know someone who is, please contact me (Talib Jetha) immediately on:
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Linkedin: https://www.linkedin.com/in/talibjetha/