Beschreibung
German Speaking Verification engineer UVM/eUVM
An exciting opportunity has arisen for a German speaking Verification engineer to join well established blue chip organisation based at their prestigious offices in Munich.
As a German Speaking Verification engineer
You will be Familiar with SV or Specman
* Have Very good knowledge with respect to UVM or eUVM
* Have Very good understanding of object-oriented programming principles
* Able to derive verification plans from specifications and requirement data bases
* Experienced in building up block or chip level environments including verification components, constraint random stimulus, assertion- as well as scoreboard-based checks and functional coverage models
* Familiar with typical simulator and debugging environments (eg Cadence Incisive)
* Able to run and analyze regressions using verification cockpits (eg Cadence Vmanager)
* Proficient user of data management tools (eg ClearCase or git)
* Able to perform Formal Verification using a typical tool (eg Onespin360)
* Basic understanding of RTL design and behavioral modelling with VHDL and Verilog
* Proficient user of Linux-based OSs and typical Scripting languages (eg Python or Perl)
* Able to work with a typical bug tracking platform (eg Atlassian JIRA)
Soft Skills
Communication
* Able to abstract technical details
* Open to communicate with people on and off site
* Open communication style
* A very good level of spoken and written English (at least B2 level)
Team player
* Committed to the team and task
* Helping team members, sharing knowledge
Self motivated
* Embracing the task
* Highlight potential issues
* Regular reporting
* Clean and organized working style
* Following and improving processes
Able to follow corporate reporting standards
So if you are German speaking verification engineer looking for your next contract apply now.