Beschreibung
My client based in Munich, are looking for a Semiconductor Design Engineer with experience in Design For Test (DFT) projects. This is a 6 month assignment on site in the offices in Munich and the role will be conducted in English.The engineer will need to have experience in ATPG (Automatic Test Pattern Generation) using Mentor Tools, re simulation of scan patterns and scan synthesis using Synopsys Tools. They will need to have experience in Digital Simulation and be able to work in VHDL / Verilog with good knowledge of the digital design flow