Profilbild von Shripad Nagarkar Digital Design and Verification Engineer (Digital IPs, SOC and ASIC) aus Muenchen

Shripad Nagarkar

verfügbar

Letztes Update: 05.05.2014

Digital Design and Verification Engineer (Digital IPs, SOC and ASIC)

Abschluss: nicht angegeben
Stunden-/Tagessatz: anzeigen
Sprachkenntnisse: deutsch (gut) | englisch (verhandlungssicher) | hindi (Muttersprache)

Skills

Final Qualification: Master of Science in Electrical Engineering
Professional Experience: Corporate 8 years + 1 year visiting researcher at MIT


PROFESSIONAL SUMMARY
• Proven ability in transforming product requirements into designs under tough time constraints, while working with cross-functional teams located on different sites
• Expert in low power IP and SoC level design. Designing and integrating IPs with focus on area, power and testability
• Deep knowledge about SoC product development flows, methodologies and tools
• Excellent understanding of processor, cache memory and debug architectures. Cache architecture invention patented under `Customizable memory indexing functions´ (patent number 7856529)
• Excellent understanding of synthesis, STA and DfT
• Familiar with JTAG, scan based tests and ATPG
• Adept in creating verification plans, reusable verification IPs, gate level simulation and debugging


SKILL SET
• HDL: Verilog, VHDL
• HVL: SystemC, Specman (basic training from cadence), SystemVerilog (basics)
• Front end design tools: Cadence IUS, Atrenta Spyglass Lint/DFT/CDC, Cadence Encounter RC, Cadence Encounter Test, Cadence LEC
• Protocols: AMBA-AHB and APB, USB 2.0, UART, SPI
• Programming languages/scripting languages: C, C++, assembly language, TCL, Perl, shell script
• Repository tools: SVN, Design sync, CVS
• Documentation: MS-Visio, Latex, Frame Maker
• Operating systems: Windows, Linux, Solaris

Projekthistorie

auf anfrage

Reisebereitschaft

Verfügbar in den Ländern Deutschland
sofort
Profilbild von Shripad Nagarkar Digital Design and Verification Engineer (Digital IPs, SOC and ASIC) aus Muenchen Digital Design and Verification Engineer (Digital IPs, SOC and ASIC)
Registrieren