Embedded Software Enginer

June 2017- Present
Research & Development Engineer / Synopsys Inc., Sri Lanka
Synopsys Zebu Ethernet Transactor (https://www.synopsys.com/verification/emulation/zebu-solutions.html)

April 2016 – June 2017
Corporate Application Engineer / Synopsys Inc., Sri Lanka

10/2014 – 03/2015
Trainee Electronic Engineer / Advanced Engineering Technologies (Pvt.) Ltd, Sri Lanka
Primarily worked on development of FPGA based Tea –Color sorting machine, and responsibilities were to develop algorithms and systems for different processes to be executed in FPGA, while processing Tea- color sorter.

• 2D Fast Fourier Transformation
  • Research based approach taken for choosing best algorithm for FPGA implementation (Radix -2, Radix 4, Mix Radix)
  • Radix -2 algorithm verification by implementation of C++ program.
  • Radix -2 Implementation of using serialized architecture with pipelining design.
  • Used fixed point numbering system for calculations
  • Implementation based on Altera Stratix –IV FPGA board. Hence used in build IIP cores for multiplication and accessing DRAM blocks.
  • Able to process 4K images at 80Fps rate
• Serial data communication between FPGA with CRC error checking.
  • Ability to send data at 50 Mbps for 1m distance
  • Ability to send 1024 bits packets of data without error
  • Tested on Altera Stratix –IV, Altera DE-0, and Altera DE – 115 FPGA boards.
  • Able to handle any length of CRC polynomial. Polynomial must be entered during the synthesis.
  • Only 3 pins for communication ( Data pin, Clock pin, Ground wire)
  • Use of clock gating mechanism for save energy
• AES ECB encryption implementation on FPGA
  • Supports standard key sizes (128bit, 192bit, 256 bit)
  • Simplified multiplication and adding algorithms to optimize area ( After analyzing output of multiplication and addition, it can be simplified)
  • Pipelined architecture for improve performance, 1byte/clock throughput

Projects as an Undergraduate ASIC implementation of 100Gbps PCS (Physical Coding Sub layer)
The final year project for ASIC implementation of 100Gbps PCS (Physical Coding Sub layer) layer compliant to IEEE802.03 standard. This project had three main components to be delivered.

• Soft RTL core verified with simulation
• Verified PCS core with FPGA emulation
• ASIC implementation of hard IP

First task was completed Verilog HDL based design. After lengthy study of IEEE standard for Ethernet (CL 82), PCS core was implemented. Architecture was designed in such a way that, maintaining constant data rate while introducing PCS layer specific data blocks such as Alignment markers, and lane distribution/reordering. This soft RTL code written as a synthesizable code and verified with simulations using myHDL(Python based HDL simulation) environment.
Second task was done using Xilinx VC709 FPGA board. The design was verified 40Gbps Speed (Limitation was because Xilinx VC709 board had only 4 SFP+ ports 10Gbps GTH (Gigabit Transceivers) lanes).  The used architecture to verify the design was based on software/hardware co-emulation based approach.  This approach was taken because of the high data rate to be managed and verified.

• FPGA board is connected to PC via PCIe Gen 3 port.
• Used RIFFA framework to manage the connection between Software and FPGA. This acted as MAC layer for the PCS core.
• C++ based application sends data packets to FPGA via RIFFA framework using PCIe Gen 3 Port.
• Using 4, 4K videos to generate packets and transferred them to FPGA. While packets are not available, FPGA generates IDLE(Inter Packet Gap) packets as input to PCS
• Packets go through PCS core and TX output was directed to 4 GTH transceivers, which were connected to 4SFP+ ports. SFP+ ports were looped back using high speed optical cables.
• Received packets via GTH tranceivers are received by RX side of PCS and send back to RIFFA framework.
• C++ program receives packets and reconstruct all 4 videos and play using Qt based GUI.
• C++ program also calculates data rate as well.

ASIC implementation was done using Synopsys tools.

• Synopsys Design compiler was used for synthesis
• IC compiler was used for Place and Route and to get the hard IP.
• SpyGlass (Atrenta) was used for resolving any issues prior to synthesis.
• Synopsys DFT was used to insert test registers into the design.

Control Communication Architecture for Dynamic Software and Hardware Partitioning
The final year research project of implementing a newel architecture for dynamic hardware software partitioning. This is a proof of concept to introduce this architecture using GPIO management. Introduce architecture has been verified using software simulation and hardware emulation using Altera DE2-115 FPGA.
The project had two main research components.

• Management of GPIO for controlling tasks
• Execution analysis and controlling task list based on overall system performance

To implement the system, Altera DE2-115 board was used. This board had the capability to host multiple NIOS-II processors and connect Hardware IP cores using Avalon System Bus.
The system contained 3 task processors and 1 Master processor for controlling tasks. The same task list was implemented as Digital Circuits in Verilog HDL cores and burned to FPGA as well.
Master FPGA executes tasks according to the given task list and, manages a database of execution time on processors and hardware implementation. When task are to be reused, Master processor reprogram the task execution to hardware or to processor based on availability and execution time.
FPGA based Guitar Tuner using digital signal processing
The project deliverables were to provide an easy method to tune the instrument for the musician. So the design will identify the similarity, based on the frequency of the note played and how it should be which is preset by the user. Then it will show the output by 1-10 LED scale.
Using a low pass filter to remove noise from our required signal. That increased SNR value of external musical instrument signal. Filtered signal was processed using Fast Fourier algorithm to separate frequency components of the receiving signal, to get frequencies which belongs to musical notes. Due to noise factor in signal, FFT transformed signal then passed through band pass filters using rectangular windows that resulted in good simulation results. Result was a 0-1 scaled amplitude of filtered signal. Above simulations were done using MATLAB Simulink.
For the hardware implementation, Xilinx System Generator was used in MATLAB Simulink. Using FIR compiler available in Xilinx block set, filter was created on FPGA.
Video Google Implementation
Implementation of efficient visual search of video cast as text retrieval- by Josef Sivic and Andrew Zisserman.
Open CV C++ framework was used for implementation.
Connect 6 AI
Developed algorithm (mikro C pro for PIC) to play the game connect6 and system developed in a microchip PIC micro-controller. Secured the first runner-up position in first year AI competition.
Taxi Dispatching System
Java based taxi dispatching system implementation as per software engineering course project. Project was developed using MVC architecture. This included,

• Agent for taxi dispatch
• Client Android application for drivers to receive jobs and accept jobs
• Admin control panel for managing Drivers, Customers
• Customer Web Application for ordering/Scheduling Taxies

SLRC 2012- Sri Lankan Robotics Challenge | University of Moratuwa (2012)
The contest was about simulating a moon explorer (Mother Robot) and its rover (Pathfinder Robot). The explorer deploys the rover into a grid where rover carries out extracting marked boxes and returns to explorer. In every iteration, the deployment location and the marked box locations randomly changes.

• Team member
• Awarded for complete robotic designs

Xbotix 2015 – University of Ruhuna, Sri Lanka Robotics challenge
The contest was about designing fastest line following robot with object detection. Robot has to follow the lines and find the correct path to the objects and place the objects in correct places. 

• Main programmer of the team
• Achieved 3rd Place of the competition

Arduino Programming, Electronics
GSM based Mobile Device tracking Telco App
A Telco App based on Dialog Axiata, Sri Lanka provided Telco application development platform (Ideamart). This app enable users to track their registered loved ones. For the user Android App was developed using Google Maps API to provide live tracking details. Experience as a Freelancer  Breathe Analyzer
An Embedded System with Software GUI for Police Departments. Hardware was developed using Atmega328P microcontroller to read GAS sensor for alcohol concentration of the breathe air. Algorithms were developed to match the GAS sensor characteristics based on humidity, temperature and air flow rate.
Java based GUI was developed for connecting hardware with software. Software was able to perform,

• Capturing image of the user
• Creating a database of users
• Sending Text messages and emails instantly
• Printing Receipts, Printing reports( Monthly, Weekly or Filtered data)

An embedded version was developed later based on Raspberry pi with 7 inch display, for portable usage.
Home automation System
Development of home automation system based on Arduino platform and Z-wave communication. Involved in development of sensors and actuator control development such as

• Temperature, Humidity , Rain, Soil , Current sensor monitoring and posting data to Android device
• Based on Android device inputs, activate door locks, window blinds, Door open/close

Develop communication between Android and Arduino devices using USB OTG cable.
Raspberry pi based embedded Video Player
Development of raspberry pi based video player. Videos are played based on user input via push buttons connected to Raspberry pi GPIO pins. Application developed based on Java.