Skills
3 years senior application engineering followed by 15 years consulting experience.
SystemC, C++, High Level Synthesis (3 years)
VHDL using ModelSim, Cadence NCSIM, Simulators. (12 years)
Verilog using verilogXL and NCSIM cadence simulators. (9 years)
Synthesis using Synopsys, Synergy, and Leonardo Spectrum for the following target technologies: ASIC (0.8um > 65nm), FPGA, and EPLD. (10 years)
Used Mentor Graphics HDL designer (2 years)
FPGA design using both Xilinx and Altera software (3 years)
Used Linux, SUN Solaris, HPUX, and all MS Windows Operating Systems
Written Assembler for 8,16, and 32 bit microprocessors (RISC and SISC),DSP software for the TMS 32020, C/C++, and Java.
Used SED, AWK, Perl, and TCL scripting languages (7 years)
Design of digital hardware for video compression, 68020 CPU boards, ARM RISC Microcontroller, 4 video ASICs, SDRAM memory control interface, and AXI MTL PCI VME ISA PCMCIA interfaces.
SystemC, C++, High Level Synthesis (3 years)
VHDL using ModelSim, Cadence NCSIM, Simulators. (12 years)
Verilog using verilogXL and NCSIM cadence simulators. (9 years)
Synthesis using Synopsys, Synergy, and Leonardo Spectrum for the following target technologies: ASIC (0.8um > 65nm), FPGA, and EPLD. (10 years)
Used Mentor Graphics HDL designer (2 years)
FPGA design using both Xilinx and Altera software (3 years)
Used Linux, SUN Solaris, HPUX, and all MS Windows Operating Systems
Written Assembler for 8,16, and 32 bit microprocessors (RISC and SISC),DSP software for the TMS 32020, C/C++, and Java.
Used SED, AWK, Perl, and TCL scripting languages (7 years)
Design of digital hardware for video compression, 68020 CPU boards, ARM RISC Microcontroller, 4 video ASICs, SDRAM memory control interface, and AXI MTL PCI VME ISA PCMCIA interfaces.
Projekthistorie
References from Infineon and Cadence are available on request.
Reisebereitschaft
Verfügbar in den Ländern
Deutschland
I am based in Munich and would prefer freelancer work in the Munich area.
Sonstige Angaben
Full Driving License
