VE

Venu Madhav Ega

verfügbar

Letztes Update: 08.03.2019

Digital Design and Verification - FPGA/ASIC

Abschluss: Masters
Stunden-/Tagessatz: anzeigen
Sprachkenntnisse: deutsch (gut) | englisch (verhandlungssicher)

Dateianlagen

CurriculumVitae.pdf

Skills

- 14 + years of experience in digital design targeting to several FPGA / ASIC SoC technologies
- Expertise in VHDL and Verilog RTL design, System Verilog
- Functional and Post layout back annotated timing simulation
- Tcl scripting for Synthesis and STA, 
- Assertion based auto checking test bench, test models for ADC, DAC, Flash Controller
- Code Coverage and Formal Verification
- Mentor Graphics - Modelsim, QuestaSim, HDL Designer
- Xilinx Vivado, ISE, Altera Quartus, Lattice Diamond, Microsemi Libero SoC
- Xilinx-Kintex7, Artix7, Intel/Altera - MAX-10, Cyclone-IV, Cyclone-V, Lattice-XP2, MachXO2
- Synopsys VCS, Lint Checking, DC-Compiler, PrimeTime
- JTAG UART, SPI, WB, Avalon, AMBA AXI-4, CAN, I2C, USB, SATA, EtherCAT bus interaces
-Version Control Systems - Cliosoft SOS, SVN, Git
-Debugging experience in Windows and Linux environments
-System Level debugging with Python

Projekthistorie

Available upon request.

Reisebereitschaft

Verfügbar in den Ländern Deutschland, Österreich und Schweiz
Profilbild von VenuMadhav Ega Digital Design and Verification - FPGA/ASIC aus KarlsruheOberreut Digital Design and Verification - FPGA/ASIC
Registrieren