Khawar Parvez verfügbar

Khawar Parvez

Project Management/ Teamlead/ Software/Embedded/ASIC/FPGA Design & Verification Engineer

verfügbar
Profilbild von Khawar Parvez Project Management/ Teamlead/ Software/Embedded/ASIC/FPGA Design & Verification Engineer aus Sindelfingen
  • 71063 Sindelfingen Freelancer in
  • Abschluss: Elektro/Informationtechnik (Masters) & MBA
  • Stunden-/Tagessatz: 85 €/Std.
    hängt von Projekt und Standort ab
  • Sprachkenntnisse: deutsch (verhandlungssicher) | englisch (verhandlungssicher)
  • Letztes Update: 26.11.2017
SCHLAGWORTE
DATEIANLAGEN
Fraunhoffer_Experience

Diese Anzeige ist nur für angemeldete Nutzer möglich.

Navigon Experience

Diese Anzeige ist nur für angemeldete Nutzer möglich.

TUKL & DFKI Experience

Diese Anzeige ist nur für angemeldete Nutzer möglich.

Pharmasol

Diese Anzeige ist nur für angemeldete Nutzer möglich.

Advantest Experience

Diese Anzeige ist nur für angemeldete Nutzer möglich.

Master of Business Administration

Diese Anzeige ist nur für angemeldete Nutzer möglich.

Masters of Electrical Engineering

Diese Anzeige ist nur für angemeldete Nutzer möglich.

Transceivers

Diese Anzeige ist nur für angemeldete Nutzer möglich.

System Verilog Design & Verification

Diese Anzeige ist nur für angemeldete Nutzer möglich.

PCI Express

Diese Anzeige ist nur für angemeldete Nutzer möglich.

Highspeed Memory Interface

Diese Anzeige ist nur für angemeldete Nutzer möglich.

FPGA Design Methodolgy

Diese Anzeige ist nur für angemeldete Nutzer möglich.

System Verilog Assertions

Diese Anzeige ist nur für angemeldete Nutzer möglich.

System Verilog Assertions

Diese Anzeige ist nur für angemeldete Nutzer möglich.

Business Informatic Workshop

Diese Anzeige ist nur für angemeldete Nutzer möglich.

Resume

Diese Anzeige ist nur für angemeldete Nutzer möglich.

SKILLS
Hardware
HDL & Script:
Verilog/SystemVerilog, VHDL, SystemC, TCL, Python, Ruby, Shell scripting
EDA Tools:
Xilinx Vivado, ISE, Altera Quartus,Qsys, Cadence Simvision, e-manager, e- planner Mentor graphics Questa/Modelsim, ReqTracer, Precision, Synopsys Synplify Pro, Verdi3
ASIC/FPGAs:
Custom processor chips, Xilinx Ultrascale Virtex, Kintex, Artix, 7-series Virtex, Kintex, Artix, Zynq, Virtex6, Virtex5, Spartan6, Altera Arria10, Max10, Stratix5/4, Cyclone5/4/3
CPU/MCUs:
Arm Coretex A9, PowerPC, Microblaze, NIOS, Freescale M68HC05/08
Technologies:
High speed transceivers, PCI-Express, SPI,I2C, UART,SerialLite2, Parallel backplane buses
CAN, Ethernet, DFT, Timing analysis STA, High speed RTL synthesis and optimization, LVDS, DDR2/3 LPDDR2/3 memories, QSPI Flash, ADC/DAC, EEPROM, Amplifiers, Voltage regulators, Functional/Timing simulation, System level chip verification, PCB layout analysis, Semiconductor technologies

Software
Languages:
C/C++, C#, Java, Javascript, SQL, HTML/XML/CSS,PHP, Perl
IDE/Compilers:
MS visual studio, GNU gcc/g++, make/gmake/qmake, Eclipse, Netbean, QT4 designer, Matlab
Editors:
Gvim, Emacs, Notepad++, Ultraedit, Nedit
Version Control:
Perforce, Clearcase, Subversion, CVS, GIT
 Applications:
MS Office, Open Office, Adobe Photoshop, CorelDraw, Adobe Dreamweaver
Technologies:
MFC, STL, Win32 API, OOA/D, Design Pattern, UML, OpenGL, wxWidgets, QT, TK ruby, OpenCV, Qhull, Java J2EE, Lucene, Lius, PdfBox, Image processing toolbox of Matlab, SQL server, Oracle API, ODBC, MS Access, MySql, CakePHP, CMS Joomla, Wordpress, Opencart, Zend Framework, Magento
PROJEKTHISTORIE
Research and Development                 


            
Advantest Europe GmbH Böblingen, Germany
Team Manager's Consultant /Team Lead digital design team 2014 – Present
  • As team manager consultant in System-On-Chip business group, coordinated and monitored the development activities of offshore digital design teams in Japan, USA, local digital design team in Germany, and outsource partners from India. Communicated the development plans and collecting the status information on different projects to higher level management.
  • Took the responsibility of on time delivery of technical solutions for ATE industry products.
  • Hosted various knowledge sessions, meetings for team and cross functional teams.
  • Led SCRUM sessions and defined the monthly and daily sprints.
  • Provided the clear and concise analysis and recommendations to team management.
  • Assisted team manager with project reports(ticker) updates for higher level management
  • As team lead in digital design group of System-On-Chip business group, I led the research and development projects for various high end and low end Advantest products for customers from diverse industry sectors. The research and development projects range from FPGA, embedded systems, ASIC, micro-controller and software designs.
  • Led the team of 9 engineers to develop the digital designs of new generation 93K and T2000 tester platform and led product qualification with cross-functional teams (SW/ HW R&D, testing, service and support, operations).
  • Made the project development plan, product definitions were prioritized and documented into project planning part of FPGA development plan. Timely check of milestone and deadlines against solution designs helped to address potential assembly issues which become difficult to fix at later stage. Met the project deadlines in timely manner and involved the project stack holders and core team members to control and monitor the desired out comes.
  • Coordinated the cross functional team’s development activities to achieve the organization’s objective of common backend software and hardware components. Facilitated team members to contribute their work effectively to organization’s initiative by motivating and bringing them together in different software hardware common meetings.


Advantest Europe GmbH Böblingen, Germany
Expert Digital Design/Verification Engineer 2007 – Present
  • As expert digital design engineer in hardware design team of System-On-Chip business group, developed high performance RTL designs targeting diverse FPGA families of Xilinx and Intel/Altera vendors. These designs range from simple glue logic to complex high speed transceiver designs. Some of various designs are data path, high speed memory interfacing of DDR2/3, LPDDR2/3, embedded processor interfaces, ADC/DAC controllers, SPI, I2C, PCI endpoint, SERDES, and high speed transceiver interfaces from Xilinx and Altera FPGA families e.g. “Arria10, Stratix5, Virtex7,Kintex7, Ultrascale Virtex/Kintex”. The electrical signals were realized in LVDS, CML, and LVPECL standards.
  • Development of Verification and Test plans. Performed functional as well as transactional level verification of digital designs based on RTL, post-synthesis, and post place-route netlist. The full system hierarchy included analog component’s models, micro-processors, FPGAs, and other ASIC bus functional models.
  • Universal verification methodology UVM, TLM, SystemC, C++, SystemVerilog/DPI/OOP, constraint random stimuli, and assertions based verification were deployed. Further block level and chip level test benches were developed using directed stimuli approach in systemVerilog/Verilog/VHDL languages. Coverage databases were managed, analyzed and linked to verification and test plans in different EDA vendor tools e.g. Cadence, Mentor Graphics.
  • Devised various embedded system solutions for hardware turn-on, FPGA configuration, QSPI flash access, board management tasks including alarm handling, power status monitoring, and for various time consuming tasks. The embedded processors e.g. “Arm Coretex A9, PowerPC, Microblaze, NIOS” from Xilinx and Altera FPGA devices were used for different projects. Experienced in verification of ARM based SoC.
  • Standardized on-chip and off-chip components communication buses for system on chip designs.
  • Setup functional simulation and pre/post route timing simulation for new generation 93K platform instruments using Modelsim and Cadence tool chains.
  • Performed the static timing analysis on high performance RTL designs utilizing gigabit transceivers, PCIe protocols, and various other parallel interfaces.
  • Integrated 93K smartest and embedded test processor interfaces over LVDS, CML standards to both Xilinx and Intel/Altera FPGA devices.
  • Turned-on and debugged hardware issues using logic analyzers, Xilinx’s chipscope, and Intel/Altera’s signal tap.
  • Automated digital design and simulation regression test flows using industry standard TCL for EDA tools.
  • Documented the interface specifications and defined address maps for FPGA designs.


Navigon GmbH Würzburg, Germany
Software Engineer 06/2007 – 09/2007
  • Developed core components of navigation software of company Navigon. Further owned, implemented and documented the new interfaces for framework components.
  •  Integrated the incremental code changes from feature branches to mainstream branch and prepared release branch of framework components. Perforce P4v version control system was deployed for this project.
  • Enhanced the maps archiver tool of navigation software.
  • The C/C++ with MS visual studio under Windows OS was used as main development platform.


Fraunhofer ITWM (Institut für Techno- und Wirtschaftsmathematik) Kaiserslautern, Germany
Scientific Research Assistant 07/2006 – 06/2007
  •  Implemented complex image computation and analysis algorithm for commercial MAVI software of ITWM.
  • Integrated MAVI libraries and developed a complete module for image processing and surface analysis of microstructures like concrete materials, metal, and foam.
  • The C/C++ with GNU tool chain under Linux OS was used as main development platform


Pharma SOL Kaiserslautern Germany GmbH Kaiserslautern, Germany
Software Solution Provider 09/2006 – 03/2007
  • Provided consulting services, programming solutions for database applications and other client/server standalone applications to Pharmaceutical SOL firm, namely Oracle9i client server application development.
  • Utilized OCCI Oracle server application interface to develop data processing tools. Programmed tool for analysis and processing of organizational and hospital database logs for performance checks. Developed tool for saving users credential to database server in encrypted form.
  • The C/C++ with GNU tool chain under Linux OS was used as main development platform.


DFKI (Deutsche Forschungszentrum für Künstliche Intelligenz) Kaiserslautern, Germany
Scientific Research Assistant 09/2006 – 03/2007
  • Developed the graphical user interface for image based personal computing application. The wxWidget library under Linux platform was used for front-end and C++ was the main programming language for back-end. Utilized OpenCV image processing library algorithms for various dialog options of application.
  • Programmed the indexing and searching feature of document browser application using Java as main programming language and deployed various Java packages to implement required features.
  • The C/C++ /wxWidgets with GNU tool chain and Java/Java Packages/Eclipse under Linux OS were used as main development platform.


Technical University of Kaiserslautern, Electronic Design Automation Kaiserslautern, Germany
Scientific Research Assistant 03/2005 – 07/2006
  • Performed formal hardware verification of digital systems like Tri-Core TM32-bit CPU, module interconnections, bus protocols such as AMBA bus.
  • Verified MULT instruction set of Infineon’s Tri-Core 32-bit unified CPU Core 2.0 using bounded model checked GateProp (formal verification tool from Infineon) by formulating properties in tool specific languages VLI/VHI.
  • Developed SAT solver tool for equivalence checking of RTL level designs, and implemented backend support for MiniSat 1.12 tool.
  • Design, simulation, and synthesis of digital circuits performed interactively and by writing regression scripts to run tests overnight and manage test data.
  • The C/C++ /VLI/VHI/Shell scripts/GateProp/MiniSat under Linux OS were used as main development platform.


Trainings & Certifications
Management
  • Project Management Fundamentals
  • Fundamentals of business information technology
  • Influencing in Matrix Organization
  • Auftritt und Ausstrahlung
Technical
  • Ultrascale & Ultrascale transceivers
  • PCI express
  • Zynq
  • Vivado design suite
  • Xilinx FPGA design methodology
  • High speed memory interface
  • Altera design suite
  • System Verilog assertions
  • System Verilog design and verification

References
  • Professor Doctor Engineer Wolfgang Kunz Department of Electrical and Computer Engineering Chair “Electronic Design Automation” http://www.uni-kl.de
  • Professor Doctor Engineer Nobert Wehn Department of Electrical and Computer Engineering Chair “Microelectronic systems Design Research Group” http://www.uni-kl.de
  • Professor Doctor Thomas Breuel Head of Image Understanding and Pattern Recognition in German Research Center for Artificial Intelligence (DFKI) GmbH http://ww.iupr.org
  • Doctor Katja Schladitz Fraunhofer ITWM Kaiserslautern Germany GmbH http://www.itwm.fraunhofer.de
  • Pharma SOL Kaiserslautern Germany GmbH http://www.pharmasol.de
  • R&D Manager Navigon GmbH Germany. http://www.navigon.com
  • Advantest Germany GmbH. https://www.advantest.com/DE/index.htm
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