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Letztes Update: 06.09.2022

Project Management/ Teamlead/ Software/Embedded/ASIC/FPGA Design & Verification Engineer

Abschluss: Elektro/Informationtechnik (Masters) & MBA
Stunden-/Tagessatz: anzeigen
Sprachkenntnisse: deutsch (verhandlungssicher) | englisch (verhandlungssicher)

Skills

Hardware
  HDL & Script: Verilog/SystemVerilog, VHDL, SystemC, TCL, Python, Ruby, Shell scripting
  EDA Tools:   Xilinx Vivado, ISE, Altera Quartus,Qsys, Cadence Simvision, e-manager, e- planner Mentor graphics Questa/Modelsim, ReqTracer, Precision, Synopsys Synplify Pro, Verdi3
  ASIC/FPGAs: Custom processor chips, Xilinx Ultrascale Virtex, Kintex, Artix, 7-series Virtex, Kintex, Artix, Zynq, Virtex6, Virtex5, Spartan6, Altera Arria10, Max10, Stratix5/4, Cyclone5/4/3
  CPU/MCUs: Arm Coretex A9, PowerPC, Microblaze, NIOS, Freescale M68HC05/08
  Technologies: High speed transceivers, PCI-Express, SPI,I2C, UART,SerialLite2, Parallel backplane buses CAN, Ethernet, DFT, Timing analysis STA, High speed RTL synthesis and optimization, LVDS, DDR2/3 LPDDR2/3 memories, QSPI Flash, ADC/DAC, EEPROM, Amplifiers, Voltage regulators, Functional/Timing simulation, System level chip verification, PCB layout analysis, Semiconductor technologies
 
Software
Languages: C/C++, C#, Java, Javascript, SQL, HTML/XML/CSS,PHP, Perl
  IDE/Compilers: MS visual studio, GNU gcc/g++, make/gmake/qmake, Eclipse, Netbean, QT4 designer, Matlab
  Editors: Gvim, Emacs, Notepad++, Ultraedit, Nedit
  Version Control: Perforce, Clearcase, Subversion, CVS, GIT
   Applications: MS Office, Open Office, Adobe Photoshop, CorelDraw, Adobe Dreamweaver
  Technologies: MFC, STL, Win32 API, OOA/D, Design Pattern, UML, OpenGL, wxWidgets, QT, TK ruby, OpenCV, Qhull, Java J2EE, Lucene, Lius, PdfBox, Image processing toolbox of Matlab, SQL server, Oracle API, ODBC, MS Access, MySql, CakePHP, CMS Joomla, Wordpress, Opencart, Zend Framework, Magento

Projekthistorie

07/2020 - bis jetzt
RTL Design, Test, Qualification and Optimization
(Internet und Informationstechnologie, 500-1000 Mitarbeiter)

• Custom designed DDR3-RAM Controller was tested against memory vendor specifications
• RTL Code optimization with goal to fit for different Basler camera platforms
• Consultancy on adaption of existing FPGA software interfaces
• Developed new Pixel sorter component for GPixel sensors at front-end domain
• Extended image processing pipeline in Camera to achieve higher throughput
• Adaption of 5 GigE backend and implementation of unit tests
• Pretty good image Zoom (PGI Zoom) algorithm was extended to support 4 pixels pipeline

Tools & Technologies
VHDL, SystemVerilog, Python, FPGA-Kintex family, Synopsys VCS, DevBox flavor Ubunut, Windows 10, GIT, Sourcetree, OpenOffice, Shell Scripting

12/2018 - 12/2020
Software Application and Web Services Developnent
(Internet und Informationstechnologie, >10.000 Mitarbeiter)

• Implemented micro services for critical business logic based CQ5 technology stack
• Adapted Apache Felix services to address business need
• Developed AEM components for Daimler dealer’s portal using Java, sightly
• Extended AEM widgets and UI using ECMA/Sass and REST APIs
• Added workflows to automate coordination of discrete services
• Configured static and dynamic software permissions for global and regional rolls and users
• Supported Jenkins CI/CD processes by developing jobs and troubleshooting issues
• Software deployment on Amazon cloud servers using docker containers
• DevOps activities, Jenkins, Amazon Cloud Services, Nexus deployments

Tools & Technologies
Java, SQL, Javascript ECMA, HTML/Sightly, SaSS/CSS, SourceTree, GitKraken, InteliJ, Eclipse, MS Code, Brackets, OpenOffice, Bash/Shell Scripting, Windows 10, Linux

10/2010 - 10/2020
FPGA - ASIC - Embedded - SOC Development/Verification/Validation
(Internet und Informationstechnologie, 5000-10.000 Mitarbeiter)

• As expert digital design engineer in hardware design team of System-On-Chip business group, developed high performance RTL designs targeting diverse FPGA families of Xilinx and Altera vendors. These designs range from simple glue logic to complex high-speed transceiver designs. Some of various designs are data path, high speed memory interfacing of DDR2/3, LPDDR2/3, embedded processor interfaces, ADC/DAC controllers, SPI, I2C, PCI endpoint, SERDES, and high speed transceiver interfaces from Xilinx and Altera FPGA families e.g. “Arria10, Stratix5, Virtex7,Kintex7, Ultrascale Virtex/Kintex”. The electrical signals were realized in LVDS, CML, and LVPECL standards.
• Development of Verification and Test plans. Performed functional as well as transactional level verification of digital designs based on RTL, post-synthesis, and post place-route netlist. The full system hierarchy included analog component’s models, micro-processors, FPGAs, and other ASIC bus functional models.
• Universal verification methodology UVM, TLM, SystemC, C++, SystemVerilog/DPI/OOP, constraint random stimuli, and assertions-based verification were deployed. Further block level and chip level test benches were developed using directed stimuli approach in systemVerilog/Verilog/VHDL languages. Coverage databases were managed, analyzed and linked to verification and test plans in different EDA vendor tools e.g. Cadence, Mentor Graphics.
• Devised various embedded system solutions for hardware turn-on, FPGA configuration, QSPI flash access, board management tasks including alarm handling, power status monitoring, and for various time-consuming tasks. The embedded processors e.g. “Arm Coretex A9, PowerPC, Microblaze, NIOS” from Xilinx and Altera FPGA devices were used for different projects. Experienced in verification of ARM based SoC.
• Standardized on-chip and off-chip components communication buses for system on chip designs.
• Setup functional simulation and pre/post route timing simulation for new generation 93K platform instruments using Modelsim and Cadence tool chains.
• Performed the static timing analysis on high performance RTL designs utilizing gigabit transceivers, PCIe protocols, and various other parallel interfaces.
• Integrated 93K smartest and embedded test processor interfaces over LVDS, CML standards to both Xilinx and Altera FPGA devices.
• Turned-on and debugged hardware issues using logic analyzers, Xilinx’s chipscope, and Altera’s signal tap.
• Automated digital design and simulation regression test flows using industry standard TCL for EDA tools
• Documented the interface specifications and defined address maps for FPGA designs.

Tools & Technologies
Xilinx Vivado, Intel/Altera Quartus, Modelsim/Questasim, Cadence Simvision, Verilog/System Verilog, VHDL, SystemC, C/C++, TCL, Python, Eshare, Arm processor based Zynq FPGA, Ultrascale Virtex/Kintex/Artix FPGAs, Stratix/Cyclone/Arria/Max FPGAs, Transceivers, PCIe, UART, Ethernet
Redhat Linux, Windows, SVN, JIRA

09/2012 - 04/2013
ASIC verification - Hard-macro IP verification
(Internet und Informationstechnologie, >10.000 Mitarbeiter)

Automotive System on chip - Renesas
 
This specific SOC was designed for automotive industry. Chip offers rich functional safety and embedded security features. Chip included dual CPU cores, code & data flash, external memory interface, timer arrays, serial interfaces (e.g. CAN, CSIG, Flex-Ray), A/D converter, Motor control, DMA, security functions, BIST and other relevant interfaces. UVM methodology was used to perform functional verification at system level. The verification plan was linked to coverage database using cadence’s e-planner, and cadence’s e-manager was used to manage various simulation sessions on farm machines. The functionality specific test cases were integrated into nightly run regression flows to generate coverage database for verification matrix.

Tools & Technologies
Cadence sim-vision, Cadence e-planner, Cadence e-manager, Synopsys Verdi3, UVM, system Verilog, Perl, Shell scripts, Ultra edit32, Unix

10/2011 - 10/2012
FPGA - Embedded Software Development
(Internet und Informationstechnologie, 5000-10.000 Mitarbeiter)

Processor, FPGA based Digital channel Card

This project is based on 8 ARM processors cores and Stratix-V FPGA device. Standard IPs were implemented including PCI-Express root complex, SerialLite2, eSata, USB and DDR2 memory controller’s IP. Developed Embedded system using NIOS II with standard interfaces, data-path logic to communicate with workstation, standard SPI and backplane interfaces.

Tools & Technologies
Quartus 13.1, Qsys, NIOS II IDE, SignalTap,Modelsim 10.3, make, redhat Linux, SVN, Open Office, Verilog, VHDL, SystemC, C/C++

10/2009 - 10/2010
Firmware Software Interfaces development, Debugging
(Internet und Informationstechnologie, 5000-10.000 Mitarbeiter)

DDR3/DDR2/LPDDR memory emulation at 1066 Gbps

This project is a digital channel board with 64 ARM processor cores and Xilinx Viretx-6 FPGA. Main purpose of this board is providing DDR3 DDR2 LPDDR protocol’s emulation. FPGA implementations include several standard IP and protocols and primary among them are Xilinx DDR2 controller’s IP, SPI, backplane interface, LVDS interfaces and DDR3, DDR2, LPDDR protocols. This design has data path speed of 1066 Mbps. Software interfaces development, Hardware Turn-On and debugging are also among other activities on this project. Timing Closure was a great challenge for such high-speed data path implementation. Software interface testing and debuggin

Tools & Technologies
Xilinx ISE 14.7, PlanAhead, Chipscope, Modelsim 10.3, Redhat Linux, Windows XP, SVN, OpenOffice, Gvim, Shell Scripting, Verilog, VHDL, SystemC, Perl

10/2008 - 10/2009
FPGA- RTL - Embedded Software Development/Verification/Validation/Maintenance
(Internet und Informationstechnologie, 500-1000 Mitarbeiter)

Digital high current power supply board

This ultra-high current digital power supply board has 4 channels (customized ARM processors) and provides 160 A current in gang mode to DUT board. This board has ability to measure up to 1.5 A current and 8 V voltage. Altera Cyclone device was used for controlling board’s resources. Developed backplane interface board’s data-path, relay interface board’s FPGA, functional verification Test Bench, TCL/TK based GUI tool, Ruby based debugging tool to read out firmware registers & access to low level hardware resources. In Turn-On stage software interfaces were tested and debugged using signaTap tool.

Tools & Technologies
Quartus 13.0, SignalTap, Modelsim 10.3, Windows XP, ClearCase, MSOffice, Verilog, Tcl/Tk, Ruby, Mema

10/2007 - 10/2008
FPGA Verification - Application Software Integration/Debugging/Maintenance
(Internet und Informationstechnologie, 5000-10.000 Mitarbeiter)

Digital power supply board

Multisite device power supply. Responsible for setting up the board level simulation environment for the digital part of this project which enabled our software and firmware teams to debug and fix the issues. 8 channels which can work in master-slave mode in order to provide high current and voltages. Embedded NIOS is used as sequencer. Functional and timing simulation performed using Mentor Graphics ModelSim tool. Hardware and Software co-debugging performed using Total-view and signalTap tools. TotalView and DDD debuggers helped to debug firmware and Simulation was run on Hardware IO logs to step through firmware code.

Tools & Technologies
Quartus 2.2, SOPC, Signal Tap, ClearCase, JTAG Blaster, Redhat Linux, Windows XP, Verilog, Tcl/Tk

06/2007 - 09/2007
Software Development Engineer
(Internet und Informationstechnologie, >10.000 Mitarbeiter)

Navigation System’s Sextant

Core components development in Sextant project of Navigon’s navigation software. I was owner of framework components of Sextant, responsible for developing, maintaining, bug fixing. Version control system Perforce P4v used for integrations of code to build server’s mainstream and creation of release branches of framework components. Documenting, auditing and applying other design rules to whole framework components. Implemented new interfaces for other navigation system components. Maps archive tool’s enhancement was done.

Tools & Technologies
Microsoft Visual Studio 2005, make, Perforce, Windows XP, C/C++

07/2006 - 07/2007
Software Development Engineer
(Internet und Informationstechnologie, 10-50 Mitarbeiter)

OCCI Oracle server applications

Provided Consulting Services, programming solutions for database applications and other client/server standalone applications to Pharmaceutical SOL firm. OCCI Oracle server application interface was used to develop tools which could save bulk database of hospital and organizations to central server. Programmed tool for Analysis of organizational database logs for performance checks. Developed tool for saving users credential to database server in encrypted form. Oracle9i client Server Application development was also part of my activities.

Tools & Technologies
Oracle9i, ODBC, make, MS Visual Studio 6.0, Windows XP, C/C++, SQL

07/2006 - 06/2007
Software Development Engineer
(Internet und Informationstechnologie, >10.000 Mitarbeiter)

MAVI

Developed tools for Image Processing and Analysis and surface analysis of microstructures concrete material, metal, foam.
Implementations for complex image computation and analysis algorithms. Integrated Commercial software MAVI (ITWM) libraries, developed a complete Module which was used in MAVI.
Being working as a competent developer within a software development team enhanced my team working skills.

Tools & Technologies
Mavi software, GCC/G++, gmake, Linux, Emacs, C/C++

09/2006 - 03/2007
Software Development Engineer
(Internet und Informationstechnologie, 1000-5000 Mitarbeiter)

IPET

Developed BMBF funded project IPET, Image Base Personal Computing Tools. Design and Implementation of Graphical user Interface for CanonA620 camera using wxWidget library under Linux operating system. Optimized and enhanced the IPET project’s demonstration software. C++ and Java were the mainstream development languages. Development of document browser project, Indexing and Searching feature integrated to our application. Secondary role also included System Administrator of RedHat Linux, Ubuntu (edge).

Tools & Technologies
wxWidgets, OpenCV, LECENE, CanonA620 controller, make, Linux, Ubuntu
C/C++, Java

09/2005 - 06/2006
Software and RTL Code Development in Research Project
(Sonstiges)

INFINEON Tri-Core TM2 32-bit Unified CPU Core 2.0 verification

Development of SAT Solver for Equivalence Checking of RTL level design. Backend support for INFINEON’s formal verification tool GateProp was programmed. SAT solver based property checking using MiniSat 1.12. Backend support for MiniSat tool programmed. Wrote shell script to run overnight Regression test and management of test data.

Tools & Technologies
GateProp, MiniSat, GCC/G++, make, Linux, Emacs, C/C++, VLI, VHI

03/2005 - 09/2005
Software and RTL Code Development in Research Project
(Sonstiges)


INFINEON Tri-Core TM2 32-bit Unified CPU Core 2.0 verification
 
Formal Hardware Verification of Digital Systems including Tri-Core architectures, Module interconnections, Bus protocols e.g AMBA BUS protocol. INFINEON’s Tri-Core TM2 32-bit Unified CPU Core 2.0 Instruction set MULT was formally verified using INFINEON’s Bounded Model Checker GateProp. Formulation of properties for model checker tool. Design, Simulation and Synthesis of Digital Circuits.

Tools & Technologies
GateProp, MiniSat, GCC/G++, make, Linux, Emacs, C/C++, VLI, VHI

Reisebereitschaft

Verfügbar in den Ländern Deutschland, Österreich und Schweiz
Profilbild von Anonymes Profil, Project Management/ Teamlead/ Software/Embedded/ASIC/FPGA Design & Verification Engineer Project Management/ Teamlead/ Software/Embedded/ASIC/FPGA Design & Verification Engineer
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