Beschreibung
We are looking for a
Verification Engineer (m/f)
Reference: -en
Start: 10/14
Duration: 6 MM++
Place: in Bavaria
Branch: Herstellung von sonstigen elektronischen Bauelementen
Your tasks:
- top level digital SOC verification for an ASIC chip project
Your qualifications
- Specman UVM
- E Language
- German or English
- nice to have experience with 2D graphics or video
Skills:
- Hardware developer
Keywords: uvm specman verifikation verification asic rtl